CASC: A Cache-Aware Scheduling Algorithm For Multithreaded Chip Multiprocessors

In this paper we propose CASC, a cache-aware operating system scheduling algorithm for multithreaded chip multiprocessors (CMT). CMT is emerging as a popular architecture for server platforms, and most major hardware manufacturers plan or already have released CMT processors. It is the job of the operating system to manage the shared resources of the hardware, and the second-level (L2) cache is a critical shared resource in CMT processors. We propose an operating system scheduling algorithm, CASC, that improves management of the L2 cache. CASC works by co-scheduling threads that collectively achieve a low L2 miss rate and by giving priority to threads that do not require much space in the L2 cache. In this paper we describe the design of CASC and its implementation in Solaris 10. We show that CASC reduces L2 miss rates by 15-46% and achieves improvement in processor throughput of 28-50%.